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��aH���$���H�����aH�߃�?Y[]A\A]A^A_������)A1����H�޿�5A1�H�������H�޿�5A1�H����?������aH��뮿#A1�����H��H��H��H����@��H��w4�$�DA�0�a�!��a����a����a��p�a��@�a�h���H��I��H��H��,I��	H���A��H����H��H��*H��(I��I���I��I��	�I��4I��8I��;����A��1�I��?��5AA��A��A������E��uH��=��uH���5A1�H��.��?���D��D��5A1�����1��6A����A��w+B�$�DA�6A�!�16A��76A��J6A��Q6A��\6A1����E��tZ[]A\A]A^A_�e6A1��s���X[]A\A]A^A_Ã�t�����t1���u0H�1�H��tH�ҰxH�@H!�H����Ѓ��H��������u;����t3�WA����w(��$��DA����	��1ҍRЉ�ATUS���SH��0�j���K����%�H����I��1�D9��H�|$�ھ�GA1��j��H�|$1���i�������u3�d���8u�޿�GA1����H�t$��GA1��޽���H�t$�����i��H��tH�t$��GA�,H�t$����H�L$�h��H��tH�t$�HA1��~����=H�t$�����i��H��tH�t$�'HA��D$u�޿QHA1������f������H��0[]A\�R��HA��A�z���H��H�a3!tH��������yH�5L3!��HA�3��HA��A�E���H��H�$3!t)H�������yH�53!��HA1�踼����!i��X�H�=�2!��AWAVI��AUATM��USI��A��H�����L�D$x��H�|$��1��A�`����H�|$��1��kA�K���H�T$H�|$L��IA1���-���H�T$H�|$ �A1�����H�|$�qb����xH�|$(��.A1����Hc�H�T$�kAH�|� 1��k�ط���CD�⾭AH�H�|� 1�迷���CL���LIAH�H�|� 1�覷���CL��UIAH�H�|� 1�荷���CH�T$�fIAH�H�|� 1��r����CL��qIA��H�Hc�H�|� 1��S���H��$H�|� �{IA1�1��8���H�=�1!H�T$ Hc�A�L�@1�1�H�D� �L��H�|� H���ha��9��H�|$�Za��H���[]A\A]A^A_�H�=(1!��AWAVA��AUATE��USA��A��H�����D�D$x��H�|$��1��A虶���H�|$��1��kA脶��PAUD��D�L$H�T$(E��H�|$ ��IA1���[���H�T$(H�|$0�A1��E���H�|$(�`����ZYxH�|$(��.A1��� ���Hc�H�T$�kAH�|� 1��k�����CD�⾭AH�H�|� 1�����CD����IAH�H�|� 1��ҵ���CD��IAH�H�|� 1�蹵���C�T$����IAHc�H�H�|� 1�虵��H�|� D���IA1�1�胵��H�=�/!H�T$ Hc�A��IA1�1�H�D� ���H�|� H���_��9��H�|$�_��H���[]A\A]A^A_�R��IA��A肰��H��H�q/!t)H��������yH�5\/!��IA1������^e��X�H�=</!��AUATA��USH��A��H����x��H�|$��1��A諴���H�|$��1��kA薴��H�T$�*JAH��1���}���H�T$H�|$�A1��g���H�|$�^��E��xH�|$D��.A1���B���Hc�H�$�kAH�|�1�D�c�&����CD�꾭AH�H�|�1��
����CH�U�[JAH�H�|�1����CH�U�DJAH�H�|�1��ٳ���CH�U�NJAH�H�|�1�迳���CH�U�XJA��H�Hc�H�|�1�蟳��H�UPH�|��gJA1�1�舳��H�=�-!H�T$Ic�A��A1�1�H�D����H�|�H���]��A9��H�<$�]��H�ĸ[]A\A]�f.�f�AWAVA��AUATL�%�� UH�-�� SI��I��1�L)�H��H���]��H��t�L��L��D��A��H��H9�u�H��[]A\A]A^A_�ff.���f.�@H�Q� H��tH�1��b��f.�1�1��wb���H��H����`��H����`��H��H���Valid CPUs:not finished?
CPU %u
BANK %d
TSC %#llx
RIP %#02x:%#llx
MISC %#llx
ADDR %#llx
MCGSTATUS %#llx
PROCESSOR %u:%#x
TIME %llu
SOCKETID %u
APICID %u
MCGCAP %#llx
Timeout waiting for exception on other CPUsTHERMAL EVENTACPI/APEI reported errorUnknown vendorUndecoded extended event %xBANK %dCPU %d %s TSC %llx %sRIP%s %02x:%llx
MISC %llx ADDR %llx TIME %llu %sSTATUS %llx MCGSTATUS %llx
MCGCAP %llx APICID %x SOCKETID %x PPIN %llx
MICROCODE %x
CPUID Vendor %s Family %u Model %u Step %u
/proc/cpuinfovendor_id : %63[^
]cpu family : %dmodel : %dcpu MHz : %lfflagsAuthenticAMDERROR: AMD Processor family %d: mcelog does not support this processor.  Please use the edac_mce_amd module instead.
HygonGenuineERROR: Hygon Processor family %d: mcelog does not support this processor.  Please use the edac_mce_amd module instead.
GenuineIntelwarning: Cannot parse /proc/cpuinfo
warning: Cannot open /proc/cpuinfo
Unknown CPU type vendor %u family %u model %uForced cputype %s does not match cpu type %s from mcelog
no data in mce record
mcelog readWarning: MCE buffer is overflowed.
Hardware event. This is not a software error.
MCE %d
warning: %lu bytes ignored in each record
consider an update
mcelog.c(pfd->revents & 0x001) != 0RIP: %s
(Fields were incomplete)
WARNING: with --dmi mcelog --ascii must run on the same machine with the
     same BIOS/memory configuration as where the machine check occurred.
mcelog: mce: [Hardware Error]:CPU CPU %u: Machine Check%*[ :Ec-x]%16Lx Bank %d: %016Lx%nCPU %u BANK %u%nCPU %u %u%nMCGSTATUSMCGSTATUS %llx%nRIPRIP !INEXACT!%02x:<%016Lx> {%99s}%nTSCTSC %llx%nADDRADDR %llx%nMISCMISC %llx%nPROCESSORPROCESSOR %u:%x%nTIMETIME %llu%n%10s %10s %u %u:%u:%u %u%nMCGCAPMCGCAP %llx%nAPICIDAPICID %x%nSOCKETIDSOCKETID %u%nCPUIDCPUID Vendor %30s Family %u Model %u
HARDWARE ERROR(XEN)The hardware reports a non fatal, correctable incident occurred(XEN) Bank %d: %llx at %llxUsage:

  mcelog [options]  [mcelogdevice]
Decode machine check error records from current kernel.

  mcelog [options] --daemon
Run mcelog in daemon mode, waiting for errors from the kernel.

  mcelog [options] --client
Query a currently running mcelog daemon for errors

  mcelog [options] --ascii < log
  mcelog [options] --ascii --file log
Decode machine check ASCII output from kernel logs

Options:
--version           Show the version of mcelog and exit
--cpu CPU           Set CPU type CPU to decode (see below for valid types)
--intel-cpu FAMILY,MODEL  Set CPU type for an Intel CPU based on family and model from cpuid
--k8                Set the CPU to be an AMD K8
--p4                Set the CPU to be an Intel Pentium4
--core2             Set the CPU to be an Intel Core2
--generic           Set the CPU to a generic version
--cpumhz MHZ        Set CPU Mhz to decode time (output unreliable, not needed on new kernels)
--raw		     (with --ascii) Dump in raw ASCII format for machine processing
--daemon            Run in background waiting for events (needs newer kernel)
--client            Query a currently running mcelog daemon for errors
--ignorenodev       Exit silently when the device cannot be opened
--file filename     With --ascii read machine check log from filename instead of stdin
--logfile filename  Log decoded machine checks in file filename
--syslog            Log decoded machine checks in syslog (default stdout or syslog for daemon)
--syslog-error	     Log decoded machine checks in syslog with error level
--no-syslog         Never log anything to syslog
--logfile filename  Append log output to logfile instead of stdout
--dmi               Use SMBIOS information to decode DIMMs (needs root)
--no-dmi            Don't use SMBIOS information
--dmi-verbose       Dump SMBIOS information (for debugging)
--filter            Inhibit known bogus events (default on)
--no-filter         Don't inhibit known broken events
--config-file filename Read config information from config file instead of /etc/mcelog/mcelog.conf
--foreground        Keep in foreground (for debugging)
--num-errors N      Only process N errors (for testing)
--pidfile file	     Write pid of daemon into file
--no-imc-log	     Disable extended iMC logging
--is-cpu-supported  Exit with return code indicating whether the CPU is supported
--max-corr-err-counters Max page correctable error counters
--help	             Display this message.
%i,%iUnknown Intel CPU
Unknown CPU type `%s' specified
Cannot open config file %s
Cannot open input file `%s': %s
dump all bios
pages
mcelog %s
CPU is unsupported
Cannot open logfile %srun-credentialsglobalfilter-memory-errorsCannot open `%s'MCE_GET_RECORD_LENMCE_GET_LOG_LENCannot change group to %dCannot change user to %ddaemonCannot open pidfile `%s'logfilek8p4genericcore2intel-cpuignorenodevno-filterno-dmidmi-verbosecpumhzsyslog-errordump-raw-asciino-syslogversionconfig-fileforegroundnum-errorspidfiledebug-numerrorsno-imc-logmax-corr-err-countershelpis-cpu-supportedMCA:*MCi_MISC register valid*MC? status*Unsupported new Family*Kernel does not support page offline interfaceCyrixUMCvendor 4Centaurvendor 6TransmetaNSCp6olddunningtonxeon74xxxeon7400xeon5500xeon5200xeon5000xeon5100xeon3100xeon3200core_i7core_i5core_i3nehalemwestmerexeon71xxxeon7100tulsaintelxeon75xxxeon7500xeon7200sandybridgesandybridge-epivybridgeivybridge-epivybridge-exhaswellhaswell-ephaswell-exbroadwellbroadwell-dbroadwell-epbroadwell-exknightslandingknightsmillxeon-v2xeon-v3xeon-v4atomskylakeskylake_servercascadelake_serverkabylakedenvertonicelake_servericelake-dsnowridgecometlaketigerlakerocketlakealderlakelakefieldsapphirerapids_servergeneric CPUIntel PPro/P2/P3/old XeonIntel CoreAMD K8 and derivatesIntel P4Intel Xeon 5500 series / Core i3/5/7 ("Nehalem/Westmere")Intel Xeon 7400 seriesIntel Xeon 7100 seriesIntel generic architectural MCAIntel Xeon 7500 seriesSandy BridgeSandy Bridge EPIvy BridgeIntel Xeon v2 (Ivy Bridge) EP/EXHaswellIntel Xeon v3 (Haswell) EP/EXBroadwellIntel Xeon (Broadwell) D familyIntel Xeon v4 (Broadwell) EP/EXKnights LandingKnights MillATOMSkylakeSkylake serverKabylakeDenvertonIcelakeIcelake serverIcelake server D FamilyTremont microserverCometlakeTigerlakeRocketlakeAlderlakeLakefieldSapphirerapids server/dev/mcelog/etc/mcelog/mcelog.confprocess_mcefd��@{�@��@��@��@��@��@��@��@��@��@��@�@�@%�@_�@v�@��@��@��@��@��@��@
�@�@3�@=�@]�@}�@��@��@��@��@��@��@��@��@��@��@�@�@ �@+�@5�@?�@UNKNOWNProcessor %d heated above trip temperature. Throttling enabled.
Please check your system cooling. Performance will be impacted
Processor %d below trip temperature. Throttling disabled
MCG status:RIPV EIPV MCIP LMCE MCi status:
Machine check not valid
Error overflow
Uncorrected error
Corrected error by %s
Corrected error
Error enabled
MCi_MISC register valid
MCi_ADDR register valid
Processor context corrupt
Firmware may have updated this error
Threshold based error status: %s
MCA: corrected filtering (some unreported errors in same region)
%s Generic cache hierarchy error
%s TLB %s Error
%s CACHE %s %s Error
Memory as cache: Internal Timer error
Internal unclassified error: %x
BUS error: %d %d %s %s %s %s %s
IO MCA reported by root port %x:%02x:%02x.%x
Unknown Error %x
Model:FSB address parityResponse hard failResponse parityPIC and FSB data parityInvalid PIC request(Signature=0xF04H)Pad state machinePad strobe glitchPad address glitchRequest-did-not-timeoutRequest-timed-outMemory-accessReservedIOOther-transactionGenericData-ReadData-WriteInstruction-FetchPrefetchEvictionSnoopLocal-CPU-originated-requestResponed-to-requestObserved-error-as-third-partyLevel-0Level-1Level-2Level-3InstructionDataUnknownNo ErrorUnclassifiedMicrocode ROM parity errorExternal errorFRC errorInternal parity errorSMM Handler Code Access Violationgreenyellow
Large number of corrected cache errors. System operating, but might lead
to uncorrected errors soonres3eccmirroring with channel failovermirroring. Primary channel scrubbed successfullyUCNASRAOSRAR�K@�K@�K@�K@�K@�K@�K@�K@�K@L@L@5L@M@OL@iL@iL@M@�L@M@�L@M@�L@�L@M@M@M@M@M@M@\M@M@:M@:M@:M@M@M@M@M@M@:M@��@��@��@��@��@
�@�@1�@D�@\�@n�@|�@��@��@��@��@��@��@��@��@��@��@��@��@��@�@��@0�@8�@@�@H�@P�@\�@��@a�@i�@r�@�@��@��@��@��@��@��@\�@a�@e�@��@��@��@��@��@       bit%d = %s
  TLB error '%s transaction, level %s'
  memory/cache error '%s mem transaction, %s transaction, level %s'
  bus error '%s, %s
             %s mem transaction
             %s access, level %s'
  Northbridge %s
  ECC syndrome = %x
  Chipkill ECC syndrome = %x
  link number = %x
Bus or cacheCache tag  L2 cache ECC error
  %s array error
physicalvirtual  Instruction cache ECC error
  TLB parity error in %s array
  Data cache ECC error (syndrome %x) found by scrubber  Threshold error count overflow
  no decoder for unknown bank %u
%u %sUnknown threshold counterMC4_MISC0 DRAM thresholdMC4_MISC1 Link thresholdMC4_MISC2 L3 Cache thresholdMC4_MISC3 FBDIMM thresholderr cpu0err cpu1err cpu2err cpu3error found by scrubsublink or DRAM channelL3 subcache in error bit 0L3 subcache in error bit 1res12uncorrected ecc errorres23res24processor context corrupterror address validmisc error validerror enableerror uncorrectederror overflow (multiple errors)RAM ECC errorSync errorMaster abortTarget abortGART errorRMW errorWatchdog errorRAM Chipkill ECC errorDEV ErrorLink Data ErrorLink Protocol ErrorNB Array ErrorDRAM Parity ErrorLink RetryTablew Walk Data ErrorL3 Cache Data ErrorL3 Cache Tag ErrorL3 Cache LRU Errorres.i/orequest didn't time outrequest timed outlocal node originlocal node responselocal node observedgeneric participationgeneric errorgeneric readgeneric writedata readdata writeinstruction fetchprefetchevictsnoop?instructionreserveddata cacheinstruction cachebus unitload/store unitnorthbridgefixed-issue reoder"O@dO@dO@dO@dO@zO@dO@zO@<O@,P@�O@�O@�N@�N@�N@��@��@��@��@��@��@��@��@��@��@��@��@��@��@��@��@��@��@��@��@��@��@��@��@��@��@��@��@��@��@��@��@��@��@��@��@��@�@�@:�@��@��@��@��@��@��@��@��@��@��@��@��@��@��@U�@^�@g�@p�@y�@��@��@��@��@��@��@��@��@�@�@2�@C�@P�@b�@=�@��@�#A��@��@��@��@��@��@��@��@��@�@�@.�@@�@K�@b�@v�@��@�A��@��@"�@��@��@��@��@��@	�@�@-�@:�@H�@R�@]�@o�@x�@~�@��@��@��@��@��@��@��@F�@#	A�	A"�@��@A"�@��@��@��@��@��@��@��@length %d handle %x
string %s
handle %x length %d truncated
/sys/firmware/dmi/entries/%hhu-%d/rawCan't build pathname for DMI type %hhu instance %d
hnd %x size %d expected %d
entry %x disabled
RANGESrange %x-%x h %x a %x row %u ilpos %u ildepth %u
DMI_DIMMSdimm h %x width %u datawidth %u size %u set %u
/sys/firmware/efi/systab/proc/efi/systab/sys/firmware/dmi/entries/0-0/raw/dev/memCannot open /dev/mem for DMI decoding: %sSMBIOSNo valid SMBIOS entry point: Continue without DMI decoding%s: SMBIOS entry point at 0x%08lx
Cannot mmap 0x%lx for efi mode: %sCannot mmap 0xf0000 for legacy mode: %s_SM_DMI tables at %x, %u bytes, %u entries
Cannot mmap SMBIOS tables at %xCannot find SMBIOS DMI tablesKBNot enough unique address ranges. SMBIOS DIMM sanity check failedMissing locator. SMBIOS DIMM sanity check failedAmbiguous locators `%s'<->`%s'. SMBIOS DIMM sanity check failed
WARNING: SMBIOS data is often unreliable. Take with a grain of salt!
Memory device for address %llx too short %u
<%u>%hu Mhz Width %hu Data Width %hu Size %u %s
NoneDevice Locator: %s
Bank Locator: %s
Manufacturer: %s
Serial Number: %s
Asset Tag: %s
Part Number: %s
No DIMM found for %llx in SMBIOS
OtherFast-pagedStatic ColumnPseudo staticRAMBUSSynchronousCMOSEDOWindow DRAMCache DRAMNon-volatileRegisteredUnbufferedLRDIMMEDRAMVRAMSRAMFLASHEEPROMFEPROMCDRAM3DRAMSDRAMSGRAMRDRAMDDR2 FB-DIMMReserved 0x15Reserved 0x16Reserved 0x17FBD2LPDDRLPDDR2LPDDR3LPDDR4SIMMSIPChipDIPZIPProprietary CardTSOPRow of chipsSODIMMSRIMM|�@�@a�@��@�@�@!�@(�@4�@9�@=�@I�@T�@a�@l�@w�@��@�@a�@O�@~�@��@��@P�@��@��@��@��@��@��@��@��@��@��@��@�@��@�@�@�@�@��@�@��@�@	�@�@��@�@a�@�@�@ �@%�@)�@-�@�@>�@C�@X�@P�@W�@�@[at %.0f Mhz %u days %u:%u:%u uptime (unreliable)]nonstop_tscconstant_tsc/sys/devices/system/cpu/cpu%d/cpuidle/proc/acpi/processor/CPU%d/power C%d:usageusage[%d]/sys/devices/sys/devices/system/cpu/cpu%d/cpufreq/cpuinfo_max_freq��.A�C@�@FSB address parity error detectedPIC or FSB data parity errorBINIT observedMCE is observedMCE drivenReceived hard error response on split transaction (Bus BINIT)BINIT received from external busBERR on this CPUuncorrectable ECC errortwo failing bus transactions with address parity error (AERR)failure that caused IERRbus transaction received hard error responsetimeout BINIT (ROB timeout). No micro-instruction retired for some timereceived parity error on response transactioninternal BINITBQ_ERR_HARD_TYPEBQ_ERR_DOUBLE_TYPEBQ_ERR_AERR2_TYPEBQ_ERR_SINGLE_TYPEBQ_ERR_AERR1_TYPEBQ_DCU_READ_TYPEBQ_IFU_DEMAND_TYPEBQ_IFU_DEMAND_NC_TYPEBQ_DCU_RFO_TYPEBQ_DCU_RFO_LOCK_TYPEBQ_DCU_ITOM_TYPEBQ_DCU_WB_TYPEBC_DCU_WCEVICT_TYPEBQ_DCU_WCLINE_TYPEBQ_DCU_BTM_TYPEBQ_DCU_INTACK_TYPEBQ_DCU_INVALL2_TYPEBQ_DCU_FLUSHL2_TYPEBQ_DCU_PART_RD_TYPEBQ_DCU_PART_WR_TYPEBQ_DCU_SPEC_CYC_TYPEBQ_DCU_IO_RD_TYPEBQ_DCU_IO_WR_TYPEBQ_DCU_LOCK_RD_TYPEBQ_DCU_LOCK_WR_TYPEBQ_DCU_SPLOCK_RD_TYPE<%u:%llx>%s%s%llu%%s: %s
Family 6 Model %u CPU: only decoding architectural errors
Family %u Model %u CPU: only decoding architectural errors
Unknown Intel CPU type family %u model %u
unspecifiedMEMORY CONTROLLER %s_CHANNEL%s_ERR
Transaction: %s
Generic undefined requestMemory read errorMemory write errorAddress/Command errorMemory scrubbing errorReserved 5Reserved 6Reserved 7GENRDWRACRES5RES6RES7Internal machine check status reserved 16..23Internal machine check status reserved 32..56Reset firmware did not completeReceived an invalid CMPDInvalid Power Management RequestInvalid S-state transitionVID controller does not match POC controller selectedMSID from POC does not match CPU MSIDMemory transaction Tracker ID (RTId)Memory DIMM ID of errorMemory channel ID of errorMemory ECC syndromeMemory MISC reserved 25..37Memory corrected error count (CORE_ERR_CNT)Memory MISC reserved 53..56Memory byte enable parity errorMemory address parity errorMemory internal RTID invalidMemory access out of rangeMemory reserved 20Memory error in half of redundant memoryMemory write parity errorMemory ECC error occurred during scrubMemory read ECC errorQPI class and opcode of packet with errorQPI Request Transaction IDQPI Requestor/Home Node ID (RHNID)QPI miscreserved 19-23QPI Interleave/Head Indication Bit (IIB)QPI misc reserved 15QPI misc reserved 14Clock jitter detected in internal QPI clockingQPI Sender sent a failed response to receiverSender sent too many QPI flits to the receiverQPI credit type is not supportedQPI received unsupported message encodingQPI reserved 21QPI reserved 20Received QPI data packet that was poisoned by senderNumber of QPI retries exceededQPI Data packet had bad parityQPI header had bad paritymA�A�A�A�A�A�A�A�A�AAA8�@AAAUncorrectable ECC event on outgoing core 2 dataUncorrectable ECC event on outgoing core 1 dataUncorrectable ECC event on outgoing core 0 dataCorrectable ECC event on outgoing core 2 dataCorrectable ECC event on outgoing core 1 dataCorrectable ECC event on outgoing core 0 dataInternal timeout errorIntel Cache Safe Technology Queue full error
or disabled ways in a set overflowQuiet cycle timeout error (correctable)Inclusion error from core 0Inclusion error from core 1Write Exclusive error from core 0Write Exclusive error from core 1Inclusion error from FSBSNP stall error from FSBWrite stall error from FSBFSB Arbiter Timeout errorInclusion error from core 2Write exclusive error from core 2Parity data error on inbound data detectedParity error on FSB response field detectedHard Failure response received for a local transactionParity error detected during FSB request phaseMISC format %llx value %llx
Uncorrectable ECC event on outgoing FSB dataCorrectable ECC event on outgoing FSB dataEnhanced Intel SpeedStep Technology TM1-TM2 ErrorCBC OOD Queue Underflow/overflowPad logic detected a request strobe glitch or sequencing errorPad logic detected a data strobe glitch or sequencing errorData ECC event to error on inbound data correctable or uncorrectableDetected an Enhanced Defer parity error phase A or phase BData parity error on data received from Core 1 detectedData parity error on data received from Core 0 detectedFSB data parity error on inbound date detectedPartity error detected on Core 1 request's address fieldPartity error detected on Core 0 request's address fieldCorrected eventsconfig file line %d: %s
[%s] %s%s config option `%s' unparseable
Header without ending ]left over characters at end of lineconfig file line not field nor headernumericalchoice----conf%s-threshold%s-triggerTrigger `%s' not executable
%s-log%s-userUnknown user `%s' in %s:%s config entry
%s-groupUnknown group `%s' in %s:%s config entry
yestruenofalseoff�A�A#	A��@�A�AF�@�Aout of memoryCannot reopen logfile `%s'Cannot set FD_CLOEXEC flag on fdpoll table overfloweventloop.ci >= 0 && i < max_pollfdpoll errorunregister_pollcbnot enabled%u in %u%c%u %1s / %u %1s%u / %u %1s%s:
	%u total
	%s
/sbin:/usr/sbin:/bin:/usr/bin%ldSOCKET:%d CHANNEL:%s DIMM:%s [%s%s%s]%s: %sLocation %s
PATHPATH=%sTHRESHOLD=%sTOTALCOUNT=%luDMI_LOCATION=%sDMI_NAME=%sDIMM=%dCHANNEL=%dSOCKETID=%dCECOUNT=%luUCCOUNT=%luLASTEVENT=%luAGETIME=%uMESSAGE=%sTHRESHOLD_COUNT=%dUn%scorrected %s memory error count exceeded thresholdCannot account memory errors because kernel does not report socketidFallback %s memory error count %d exceeded thresholdsockdb_fallbacksockdb_memdbMemory errors
SOCKET %u CHANNEL any CHANNEL %d DIMM any DIMM %dDMI_NAME "%s"DMI_LOCATION "%s"uncorrected memory errorsdimm-tracking-enableddimmsocket-tracking-enabledmem-ce-errormem-uc-errordmi-prepopulate_Node%u_Channel%u_Dimm%uNODE %u CHANNEL %u DIMM %uNode%u_Bank%uA%u_BANK%ufailed to prefill DIMM database from DMI dataSocketserver.ccc->inbuf == ((void *)0)Did not receive credentials over client unix socket %p
rejected client access from pid:%u uid:%u gid:%u
permission denied
cc->outbuf == ((void *)0)dumpbiosallUnknown dump parameter
done
pagespingpong
Unknown command
error while reading from clientping
accept failed on client socketCannot enable credentials passing on client socketmcelog server too busy
socket-pathinitial-ping-timeoutClient socket path `%s' too long for unix socketmcelog server already running
cannot open listening socketCannot bind to client unix socket `%s'/var/run/mcelog-clientprocess_cmdclient_inputTrigger `%s' exited with status %d
Trigger `%s' died with signal %s
Cannot collect child %dRunning trigger `%s' (reporter: %s)
Too many trigger children running already
Cannot create process for triggerCannot chdir(%s) for triggerchildren-maxdirectoryCannot access trigger directory `%s'client connectclient command writeclient read/sys/devices/system/cpuCannot read cache topology from %scpu%u%s/%s/cachecache.ccpu < cachelen%s/index%dlevelshared_cpu_maplen == c * sizeof(unsigned)No caches found in sysfsCannot find sysfs cache for CPU %dUnifiedparse_cpumapread_cachesCannot read sysfs field %s/%sCannot parse number in sysfs field %s/%s
sysfs field %s/%s has unknown string value `%s'
CPU %d on socket %d%s has large number of corrected cache errors in %s %sSystem operating correctly, but might lead to uncorrected cache errors soon
CPU=%dLEVEL=%dTYPE=%sAFFECTED_CPUS=%s%uAFFECTED_CPUS=unknownyellowcache-threshold-triggerCannot access cache threshold trigger `%s'cache-threshold-logOfflining page %llx
%#llx/sys/devices/system/memory/soft_offline_pageSoft offlining of page %llx failed, trying hard offlining
/sys/devices/system/memory/hard_offline_pageOfflining page %llx failed: %s
Replacements of page correctable error counter exceed threshold %spage-error-counterCorrected memory errors on page %llx exceed threshold %spre soft trigger run for page %lldpage_pre_softpost soft trigger run for page %lldpage_post_soft triggeredPer page corrected memory statistics:
%llx: total %u seen "%s" %s%s
memory-cememory-ce-counter-replacementmemory-ce-actionKernel does not support page offline interface
memory-pre-sync-soft-ce-triggerCannot access page soft pre trigger `%s'memory-post-sync-soft-ce-triggerCannot access page soft post trigger `%s'Round up max-corr-err-counters from %d to %d
accountsoft-then-hardonlineofflineoffline-failedhA�AhA�A�A�APCU: QPI
MemCtrl: Uncorrected spare errorCorrected spare errorUncorrected patrol scrub errorCorrected patrol scrub errorHA Wrt byte enable parity errorHA Wrt buffer Data parity errorAddress parity errorMC_IMC_FORCE_SR_S3_TIMEOUTMC_MC_CPD_UNCPD_ST_TIMEOUTMC_PKGS_SAFE_WP_TIMEOUTMC_PECI_MAILBOX_QUIESCE_TIMEOUTMC_MORE_THAN_ONE_LT_AGENTMC_INVALID_PKGS_REQ_PCHMC_INVALID_PKGS_REQ_QPIMC_INVALID_PKGS_RES_QPIMC_INVALID_PKGC_RES_PCHMC_INVALID_PKG_STATE_CONFIGMC_WATCHDG_TIMEOUT_PKGC_SLAVEMC_WATCHDG_TIMEOUT_PKGC_MASTERMC_WATCHDG_TIMEOUT_PKGS_MASTERMC_HA_FAILSTS_CHANGE_DETECTEDMC_RECOVERABLE_DIE_THERMAL_TOO_HOTNo errorNon_IMem_SelI_Parity_ErrorBad_OpCodeI_Stack_UnderflowI_Stack_OverflowD_Stack_UnderflowD_Stack_OverflowNon-DMem_SelD_Parity_Errorܮ@!�@�@�@��@��@��@��@iMC, WDB, parity errorsCorrected memory read errorMC_CRITICAL_VR_FAILEDMC_ICC_MAX-NOTSUPPORTEDMC_PCIE_R2PCIE-RW_BLOCK_ACK_TIMEOUTIntel TXT errors Other UBOX Internal errors PCU internal error QPI: DDR4 command address parity erroriMC write data buffer parity errorUncorrected HA data byte enable errorUncorrected HA write data errorDDR3 address parity errorIntel QPI physical layer detected drift buffer alarmIntel QPI physical layer detected latency buffer rolloverIntel QPI link layer detected control error from R3QPIRx entered LLR abort state on CRC errorUnsupported or undefined packetIntel QPI link layer control errorRBT used un-initialized valueIntel QPI physical layer detected a QPI in-band reset but aborted initializationLink failover data self healingPhy detected in-band reset (no width change)Link failover clock failoverRx detected CRC error - successful LLR after Phy re-initRx detected CRC error - successful LLR without Phy re-initMC_MESSAGE_CHANNEL_TIMEOUTMC_CPD_UNCPD_SD_TIMEOUTMC_DMI_TRAINING_TIMEOUTMC_DMI_CPU_RESET_ACK_TIMEOUTMC_VR_ICC_MAX_LT_FUSED_ICC_MAXMC_SVID_COMMAN_TIMEOUTMC_VR_VOUT_MAC_LT_FUSED_SVIDMC_PKGC_WATCHDOG_HANG_CBZ_DOWNMC_PKGC_WATCHDOG_HANG_CBZ_UPMC_PKGC_WATCHDOG_HANG_C3_UP_SFMC_ICC_MAX_NOTSUPPORTEDMC_VID_RAMP_DOWN_FAILEDMC_EXCL_MODE_NO_PMREQ_CMPMC_SVID_READ_REG_ICC_MAX_FAILEDMC_SVID_WRITE_REG_VOUT_MAX_FAILEDMC_BOOT_VID_TIMEOUT_DRAM_0MC_BOOT_VID_TIMEOUT_DRAM_1MC_BOOT_VID_TIMEOUT_DRAM_2MC_BOOT_VID_TIMEOUT_DRAM_3MC_SVID_COMMAND_ERRORMC_FIVR_CATAS_OVERVOL_FAULTMC_FIVR_CATAS_OVERCUR_FAULTMC_SVID_PKGC_REQUEST_FAILEDMC_SVID_IMON_REQUEST_FAILEDMC_SVID_ALERT_REQUEST_FAILEDMC_INVALID_PKGS_RSP_QPIMC_INVALID_PKGS_RSP_PCHMC_HA_IMC_RW_BLOCK_ACK_TIMEOUTMC_IMC_RW_SMBUS_TIMEOUTMC_MSGCH_PMREQ_CMP_TIMEOUTMC_WATCHDOG_TIMEOUT_PKGC_SLAVEMC_WATCHDOG_TIMEOUT_PKGC_MASTERMC_WATCHDOG_TIMEOUT_PKGS_MASTERMC_BIOS_RST_CPL_INVALID_SEQMC_MORE_THAN_ONE_TXT_AGENT�@�@�@�@�@�@�@�@�@�@Ubox error MCA_PKGC_DIRECT_WAKE_RING_TIMEOUTUPI: M2M: MscodBucket1ErrMscodParErrMscodTimeoutMscodBgfErrMscodFullWrErrMscodPtlWrErrMscodDataRdErrUnrecognized request typeRead response to an invalid scoreboard entryUnexpected read responseDDR4 completion to an invalid scoreboard entryCompletion to an invalid scoreboard entryCompletion FIFO overflowCorrectable parity errorUncorrectable errorInterrupt received while outstanding interrupt was not ACKedERID FIFO overflowError on Write creditsError on Read creditsScheduler errorError eventUncorrected address parity errorWDB read parity errorAny HA read errorHA write byte enable parity errorHA write data parity errorLink Layer Tx Parity ErrorLink Layer reset initiated while protocol traffic not idleLink Layer Reset still in progress when Phy enters L0Rx Header-or-Credit BGF credit overflow/underflowunexpected Tx Protocol flit (EOP, Header or Data)Routeback Table errorRF parity errorUnexpected Retry.Req flitUnexpected Retry.Ack flitUC Phy Initialization FailureUC Phy detected drift buffer alarmUC Phy detected latency buffer rolloverUC LL Rx detected CRC error: unsuccessful LLR: entered abort stateUC LL Rx unsupported or undefined packetUC LL or Phy control errorUC LL Rx parameter exchange exceptionUC LL detected control error from the link-mesh interfaceCOR Phy initialization abortCOR Phy resetCOR Phy lane failure, recovery in x8 widthCOR Phy L0c error corrected without Phy resetCOR Phy L0c error triggering Phy ResetCOR Phy L0p exit error corrected with Phy resetCOR LL Rx detected CRC error - successful LLR without Phy ReinitCOR LL Rx detected CRC error - successful LLR with Phy ReinitMCA_DMI_TRAINING_TIMEOUTMCA_DMI_CPU_RESET_ACK_TIMEOUTMCA_MORE_THAN_ONE_LT_AGENTMCA_BIOS_RST_CPL_INVALID_SEQMCA_BIOS_INVALID_PKG_STATE_CONFIGMCA_MESSAGE_CHANNEL_TIMEOUTMCA_MSGCH_PMREQ_CMP_TIMEOUTMCA_PKGC_INVALID_RSP_PCHMCA_PKGC_WATCHDOG_HANG_CBZ_DOWNMCA_PKGC_WATCHDOG_HANG_CBZ_UPMCA_PKGC_WATCHDOG_HANG_C3_UP_SFMCA_SVID_VCCIN_VR_ICC_MAX_FAILUREMCA_SVID_COMMAND_TIMEOUTMCA_SVID_VCCIN_VR_VOUT_FAILUREMCA_SVID_CPU_VR_CAPABILITY_ERRORMCA_SVID_CRITICAL_VR_FAILEDMCA_SVID_SA_ITD_ERRORMCA_SVID_READ_REG_FAILEDMCA_SVID_WRITE_REG_FAILEDMCA_SVID_PKGC_INIT_FAILEDMCA_SVID_PKGC_CONFIG_FAILEDMCA_SVID_PKGC_REQUEST_FAILEDMCA_SVID_IMON_REQUEST_FAILEDMCA_SVID_ALERT_REQUEST_FAILEDMCA_SVID_MCP_VR_ABSENT_OR_RAMP_ERRORMCA_SVID_UNEXPECTED_MCP_VR_DETECTEDMCA_FIVR_CATAS_OVERVOL_FAULTMCA_FIVR_CATAS_OVERCUR_FAULTMCA_WATCHDOG_TIMEOUT_PKGC_SLAVEMCA_WATCHDOG_TIMEOUT_PKGC_MASTERMCA_WATCHDOG_TIMEOUT_PKGS_MASTERMCA_PKGS_CPD_UNCPD_TIMEOUTMCA_PKGS_INVALID_REQ_PCHMCA_PKGS_INVALID_REQ_INTERNALMCA_PKGS_INVALID_RSP_INTERNALMCA_PKGS_SMBUS_VPP_PAUSE_TIMEOUTMCA_RECOVERABLE_DIE_THERMAL_TOO_HOT�@T�@��@��@��@��@��@��@T�@��@��@��@��@��@��@T�@R�@,�@T�@T�@T�@T�@(�@1�@8�@?�@F�@M�@WDB read ECCUncorrected demand read errorCorrected Demand/Patrol Scrub ErrorCmd/Addr parityMscodDDRType=0x%llx
MscodMiscErrs=0x%llx
bank: 0x%x bankgroup: 0x%x row: 0x%x column: 0x%x
failed device: 0x%x
rank: 0x%x subrank: 0x%x
ecc mode: SDDC memory mode
SDDC
ADDDC memory mode
ADDDC
DDRT read
unknown
transient
CORR_PATSCRUB_MIRR2ND_ERRUC_PATSCRUB_MIRR2ND_ERRCOR_SPARE_MIRR2ND_ERRUC_SPARE_MIRR2ND_ERRHA_RD_MIRR2ND_ERRHA_UNCORR_RD_MIRR2ND_ERRDDR-T bad requestDDR Data response to an invalid entryDDR data response to an entry not expecting dataDDR4 completion to an invalid entryDDR-T completion to an invalid entryDDR data/completion FIFO overflowDDR-T ERID correctable parity errorDDR-T ERID uncorrectable errorDDR-T interrupt received while outstanding interrupt was not ACKedERID FI FO overflowDDR-T error on FNV write creditsDDR-T error on FNV read creditsDDR-T scheduler errorDDR-T FNV error eventDDR-T FNV thermal eventCMI packet while idleDDR_T_RPQ_REQ_PARITY_ERRDDR_T_WPQ_REQ_PARITY_ERR2LM_NMFILLWR_CAM_ERRCMI_CREDIT_OVERSUB_ERRCMI_CREDIT_TOTAL_ERRCMI_CREDIT_RSVD_POOL_ERRDDR_T_RD_ERRORWDB_FIFO_ERRCMI_REQ_FIFO_OVERFLOWCMI_REQ_FIFO_UNDERFLOWCMI_RSP_FIFO_OVERFLOWCMI_RSP_FIFO_UNDERFLOWCMI _MISC_MC_CRDT_ERRORSCMI_MISC_MC_ARB_ERRORSDDR_T_WR_CMPL_FI FO_OVERFLOWDDR_T_WR_CMPL_FI FO_UNDERFLOWCMI_RD_CPL_FIFO_OVERFLOWCMI_RD_CPL_FIFO_UNDERFLOWTME_KEY_PAR_ERRTME_CMI_MISC_ERRTME_CMI_OVFL_ERRTME_CMI_UFL_ERRTME_TEM_SECURE_ERRTME_UFILL_PAR_ERRINTERNAL_ERRTME_INTEGRITY_ERRTME_TDX_ERRTME_UFILL_TEM_SECURE_ERRTME_KEY_POISON_ERRTME_SECURITY_ENGINE_ERRRPQ parity (primary) errorDDR4 command / address parity errorHBM command / address parity errorHBM data parity errorRPA parity errorDDR_T_DPPP data BE errorDDR_T_DPPP data errorDDR link failurePCLS CAM errorPCLS data errorData ECC errorData byte enable parity errorTransaction ID parity errorCorrected read errorUncorrected read errorUncorrected metadatafatal Bucket1 errorM2M tracker parity errorM2M time outM2M clock-domain-crossing buffer (BGF) errorFull write data errorMC partial write data errorMC read data errorPhy Initialization Failure (NumInit)Phy Detected Drift Buffer AlarmPhy Detected Latency Buffer RolloverLL Rx detected CRC error: unsuccessful LLR (entered Abort state)LL Rx Unsupported/Undefined packetLL or Phy Control ErrorLL Rx Parameter ExceptionLL Detected Control ErrorPhy Initialization AbortPhy Inband ResetPhy Lane failure, recovery in x8 widthPhy L0c error triggering Phy resetPhy L0p exit error corrected with resetLL Rx detected CRC error: successful LLR without Phy ReinitLL Rx detected CRC error: successful LLR with Phy ReinitTx received LLRUnexpected Tx Protocol flit (EOP, Header or Data)Instruction address out of valid spaceDouble bit RAM error on Instruction FetchInvalid OpCode seenStack UnderflowStack OverflowData address out of valid spaceDouble bit RAM error on Data FetchClock/power IP response timeoutSMBus controller raised SMIPM controller received invalid transactionMCA_LLC_BIST_ACTIVE_TIMEOUTMCA_DMI_STRAP_SET_ARRIVAL_TIMEOUTMCA_INCOMPATIBLE_PCH_TYPEMCA_PCU_PMAX_CALIB_ERRORMCA_TSC100_SYNC_TIMEOUTMCA_GPSB_TIMEOUTMCA_PMSB_TIMEOUTMCA_IOSFSB_PMREQ_CMP_TIMEOUTMCA_SVID_MCP_VR_RAMP_ERRORMCA_FIVR_PD_HARDERRMCA_WATCHDOG_TIMEOUT_MSG_CH_FSMMCA_WATCHDOG_TIMEOUT_BULK_CR_FSMMCA_WATCHDOG_TIMEOUT_IOSFSB_FSMMCA_PKGS_SAFE_WP_TIMEOUTMCA_PKGS_RESET_PREP_TIMEOUTMCA_PKGS_SMBUS_MCP_PAUSE_TIMEOUTMCA_PKGS_SMBUS_SPD_PAUSE_TIMEOUTMCA_PKGC_DISP_BUSY_TIMEOUTMCA_PKGC_WATCHDOG_HANG_C2_BLKMASTERMCA_PKGC_WATCHDOG_HANG_C2_PSLIMITMCA_PKGC_WATCHDOG_HANG_SETDISPMCA_PKGC_ALLOW_L1_ERRORMCA_ADR_SIGNAL_TIMEOUTMCA_BCLK_FREQ_OC_ABOVE_THRESHOLDMCA_DISPATCHER_RUN_BUSY_TIMEOUT�@�@�@1�@�@1�@1�@1�@ �@1�@1�@1�@1�@1�@1�@1�@'�@��@�@�@�@	�@�@�@�@�@ݸ@ݸ@ݸ@ݸ@ȸ@ȸ@ȸ@ȸ@ϸ@ϸ@ϸ@ϸ@ָ@ָ@ָ@ָ@/dev/cpu/%d/msrWarning: cpu %d offline?, imc_log not set
Cannot open %s to set imc_log
Cannot read MSR_ERROR_CONTROL from %s
Cannot write MSR_ERROR_CONTROL to %s
Cannot re-read MSR_ERROR_CONTROL from %s
No DIMM detection available on cpu %d (normal in virtual environments)
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